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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
BRUSHLESS DC MOTOR CONTROLLER
FEATURES D Two-Quadrant and Four-Quadrant Operation D Integrated Absolute Value Current Amplifier D Pulse-by-Pulse and Average Current Sensing D Accurate, Variable Duty-Cycle Tachometer
Output voltage- or current-mode configurations. The oscillator is easily synchronized to an external master clock source via the SYNCH input. Additionally, a QUAD select input configures the chip to modulate either the low-side switches only, or both upper and lower switches, allowing the user to minimize switching losses in less demanding two-quadrant applications. The device includes a differential current-sense amplifier and absolute-value circuit which provide an accurate reconstruction of motor current, useful for pulse-by-pulse overcurrent protection, as well as closing a current control loop. A precision tachometer is also provided for implementing closed-loop speed control. The TACH_OUT signal is a variable duty-cycle, frequency output, which can be used directly for digital control or filtered to provide an analog feedback signal. Other features include COAST, BRAKE, and DIR_IN commands, along with a direction output, DIR_OUT.
D Trimmed Precision Reference D Precision Oscillator D Direction Output DESCRIPTION
The UCC3626 motor controller device combines many of the functions required to design a high-performance, two- or four-quadrant, threephase, brushless dc motor controller into one package. Rotor position inputs are decoded to provide six outputs that control an external power stage. A precision triangle oscillator and latched comparator provide PWM motor control in either
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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1
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
AVAILABLE OPTIONS TA -40_C to 85_C 0_C to 70_C PDIP (N) UCC2626N UCC3626N PACKAGED DEVICES SOIC{ (DW) UCC2626DW UCC3626DW TSSOP{ (PW) UCC2626PW UCC3626PW
{The DW and PW packages are available taped and reeled. Add TR suffix to device type (e.g. UCC2626DWTR) to order quantities of 2,000 devices per reel. N PACKAGE (TOP VIEW) DW and PW PACKAGES (TOP VIEW)
GND VREF TACH_OUT R_TACH C_TACH CT SYNCH DIR_OUT SNS_NI SNS_I IOUT OC_REF PWM_I PWM_NI
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD AHI ALOW BHI BLOW CHI CLOW DIR_IN QUAD BRAKE COAST HALLC HALLB HALLA
GND VREF TACH_OUT R_TACH C_TACH CT SYNCH DIR_OUT SNS_NI SNS_I IOUT OC_REF PWM_I PWM_NI
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD AHI ALOW BHI BLOW CHI CLOW DIR_IN QUAD BRAKE COAST HALLC HALLB HALLA
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input voltage, BRAKE, COAST, DIR_IN, HALLA, HALLB, HALLC, OC_REF, QUAD, SYNCH, PWM_I, PWM_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD SNS_I, SNS_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD Output current AHI, ALOW, BHI, BLOW, CHI, CLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA DIR_OUT, IOUT, TACH_OUT, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into negative out of the specified terminal.
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
block diagram
28 QUAD 20 BRAKE 19 COAST 18 DIR_IN 21 DIRECTION SELECT HALLA 15 HALLB 16 HALL DECODER HALLC 17 DIR_OUT 8 PWM_NI 14 PWM_I 13 SYNCH 7 CT 6 OVERCURRENT COMPARATOR S SENSE AMPLIFIER R 22 CLOW PWM COMPARATOR OSCILLATOR RxC S R Q Q PWM LOGIC 1 X5
UDG-97173
VDD
5 VOLT REFERENCE 1.75V
2
VREF
27
AHI
25
BHI
23
CHI
26 DIRECTION DETECTOR EDGE DETECTOR
ALOW
24
BLOW
Q Q
3
TACH_OUT
OC_REF 12 IOUT 11 SNS_NI 9
5 ONE SHOT 4
C_TACH R_TACH
SNS_I 10
GND
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3
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF, R_TACH = 250 k, C_TACH = 100 pF, TA = TJ, TA = -40C to 85C for the UCC2626, and 0C to 70C for the UCC3626 (unless otherwise noted)
overall
PARAMETER Supply current TEST CONDITIONS Outputs not switching MIN 1 TYP 3 MAX 5 UNIT mA
undervoltage lockout
PARAMETER Start threshold UVLO hysteresis TEST CONDITIONS MIN 9.0 0.35 TYP 10.5 0.40 MAX 11.0 0.50 UNIT V V
5-V reference
PARAMETER Output voltage Line regulation voltage Load regulation voltage Short circuit current TEST CONDITIONS IVREF = -2 mA 11 V < VCC < 14.5 V -1 mA > IVREF > -5 mA 40 120 MIN 4.9 TYP 5 MAX 5.1 10 10 240 UNIT V mV mV mA
coast input comparator
PARAMETER Threshold voltage Hysteresis TEST CONDITIONS MIN 1.60 0.04 TYP 1.75 0.10 MAX 2.00 0.16 UNIT V V
current sense amplifier
PARAMETER Input offset voltage Input bias current Gain PSRR High-level output voltage Low-level output voltage UCC3626 Output source current UCC2626 VCM = 0 V VCM = 0 V VCM = 0 V 11 V < VCC < 14.5 V IIOUT= -100 A IIOUT = 100 A VIOUT = 2 V VIOUT = 2 V 5 4.85 60 6.3 70 500 300 10 5.00 TEST CONDITIONS MIN TYP MAX 8 15 5.15 UNIT mV A V/V dB V mV A A
pwm comparator
PARAMETER Input common mode range Propagation delay time TEST CONDITIONS MIN 2.0 75 TYP MAX 8.0 150 UNIT V ns
overcurrent comparator
PARAMETER Input common mode range Propagation delay time TEST CONDITIONS MIN 0.0 50 175 TYP MAX 5.0 250 UNIT V ns
logic inputs
PARAMETER High-level logic input voltage Low-level logic input voltage TEST CONDITIONS QUAD, BRAKE, DIR, SYNCH QUAD, BRAKE, DIR, SYNCH MIN 3.6 1.4 TYP MAX UNIT V V
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF, R_TACH = 250 k, C_TACH = 100 pF, TA = TJ, TA = -40C to 85C for the UCC2626, and 0C to 70C for the UCC3626 (unless otherwise noted)
hall buffer inputs
PARAMETER High-level input voltage Hysteresis Input current TEST CONDITIONS HALLA, HALLB, HALLC HALLA, HALLB, HALLC 0V < VIN < 5 V MIN 1.7 0.6 -25 TYP 1.9 MAX 2.1 1.0 UNIT V V A
oscillator
PARAMETER Frequency Frequency change with voltage CT peak voltage CT peak-to-valley voltage SYNCH pin minimum pulse width TEST CONDITIONS RTACH = 250 k, CT = 1nF 12 V < VCC < 14.5 V MIN 9.0 7.25 4.75 500 TYP 10.0 7.5 5.0 MAX 11.0 3% 7.75 5.25 V V ns UNIT kHz
tachometer
PARAMETER High-level output voltage/VREF Low-level output voltage High-level on-resistance Low-level on-resistance High-level ramp threshold voltage Ramp voltage CTACH charge current UCC3626 On-time On time accuracy UCC2626 RTACH = 49.9 k See Note 1 See Note 1 2.375 48 -3% -4% TEST CONDITIONS IOUT = -10 A IOUT = 10 A IOUT = -100 A IOUT = 100 A MIN 99% 0 1 1 2.5 2.500 51 2.625 53 3% 3% TYP MAX 100% 20 1.5 1.5 mV k k V V A UNIT
direction output
PARAMETER High-level output voltage Low-level output voltage TEST CONDITIONS IOUT = -100 A IOUT = 100 A MIN 4.5 0 TYP MAX 5.2 0.5 UNIT V V
output
PARAMETER Maximum duty cycle Low-level output oltage Lo le el o tp t voltage High-level High level output voltage Rise and fall time NOTE 1: tON is calculated using the formula t ON + C TACH IOUT = 2 mA IOUT = 100 A IOUT = -2 mA IOUT = -100 A CI = 10 pF V HI * V LO I CHARGE 0.0 0.0 4.0 4.7 4.8 0.1 TEST CONDITIONS MIN TYP MAX 100% 0.5 0.1 5.2 5.2 100 V V V V ns UNIT
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5
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
pin descriptions
AHI, BHI, CHI: Digital outputs used to control the high-side switches in a three-phase inverter. For specific decoding information reference Table I. ALOW, BLOW, CLOW: Digital outputs used to control the low-side switches in a three-phase inverter. For specific decoding information reference Table I. BRAKE: BRAKE is a digital input which causes the device to enter brake mode. In brake mode all three highside outputs (AHI, BHI & CHI) are turned off, while all three lowside outputs (ALOW, BLOW, CLOW) are turned on. During brake mode the tachometer output remains operational. The only conditions that can inhibit the low-side commands during brake are UVLO, exceeding peak current, the output of the PWM comparator, or the COAST command. COAST: The COAST input consists of a hysteretic comparator which disables the outputs. The input is useful in implementing an overvoltage bus clamp in four-quadrant applications. The outputs are disabled when the input is above 1.75 V. CT: This pin is used in conjunction with the R_TACH pin to set the frequency of the oscillator. A timing capacitor is normally connected between this point and ground and is alternately charged and discharged between 2.5 V and 7.5 V. C_TACH: A timing capacitor is connected between this pin and ground to set the width of the TACH_OUT pulse. The capacitor is charged with a current set by the resistor on pin R_TACH . DIR_IN: DIR_IN is a digital input which determines the order in which the HALLA, HALLB, and HALLC inputs are decoded. For specific decode information reference Table I. DIR_OUT: DIR_OUT represents the actual direction of the rotor as decoded from the HALLA, HALLB, and HALLC inputs. For any valid combination of HALLA, HALLB, and HALLC inputs there are two valid transitions; one of which translates to a clockwise rotation and another which translates to a counterclockwise rotation. The polarity of DIR_OUT is the same as DIR_IN while motoring, (i.e. sequencing from top to bottom in Table 1.) GND: GND is the reference ground for all functions of the part. Bypass and timing capacitors should be terminated as close as possible to this point. HALLA, HALLB, HALLC: These three inputs are designed to accept rotor position information positioned 120 apart. For specific decode information reference Table I. These inputs should be externally pulled up to VREF or another appropriate external supply. IOUT: IOUT represents the output of the current sense and absolute value amplifiers. The output signal appearing is a representation of the following expression: I OUT + ABS I SNS_I * I SNS_NI 5
This output can be used to close a current control loop as well as provide additional filtering of the current sense signal. OC_REF: OC_REF is an analog input which sets the trip voltage of the overcurrent comparator. The sense input of the comparator is internally connected to the output of the current sense amplifier and absolute value circuit. PWM_NI: PWM_NI is the noninverting input to the PWM comparator. PWM_I: PWM_I is the inverting input to the PWM comparator. QUAD: The QUAD input selects between two-quadrant operation (QUAD = 0) and four-quadrant operation (QUAD = 1) . When in two-quadrant mode, only the low-side devices are effected by the output of the PWM comparator. In four-quadrant mode both high- and low-side devices are controlled by the PWM comparator.
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
pin descriptions
SYNCH: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using the SYNCH feature, a resistor equal to R_TACH must be placed in parallel with CT. When not using the SYNCH feature, SYNCH must be grounded. SNS_NI, SNS_I: These inputs are the noninverting and inverting inputs to the current sense amplifier, respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also incorporated into the output in order to provide a representation of actual motor current when operating in four-quadrant mode. TACH_OUT: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus providing a variable duty cycle, frequency output. The on time of the monostable is set by the timing capacitor connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during its on-time. R_TACH: A resistor connected between R_TACH and ground programs the current for both the oscillator and tachometer. VDD: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs below 10.5 V. The input should be bypassed with a 0.1-F ceramic capacitor, minimum. VREF: VREF is a 5-V, 2% trimmed reference output with 5 mA of maximum available output current. This pin should be bypassed to ground with a ceramic capacitor with a value of at least 0.1 F.
APPLICATION INFORMATION
Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs. Table 1. Commutation Truth Table
BRAKE 0 0 0 0 0 0 0 0 0 0 0 0 X 1 0 0 COAST 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DIR_IN A 1 1 1 1 1 1 0 0 0 0 0 0 X X X X 1 1 1 0 0 0 1 0 0 0 1 1 X X 1 0 HALL INPUTS B 0 0 1 1 1 0 0 0 1 1 1 0 X X 1 0 C 1 0 0 0 1 1 1 1 1 0 0 0 X X 1 0 HIGH-SIDE OUTPUTS A 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 B 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 C 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 LOW-SIDE OUTPUTS A 0 0 0 1 1 0 1 0 0 0 0 1 0 1 0 0 B 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 C 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0
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7
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
The UCC3626 is designed to operate with 120 position sensor encoding. In this format, the three position sensor signals are never simultaneously high or low. Motors whose sensors provide 60 encoding, can be converted to 120 using the circuit shown in Figure 1. In order to prevent noise from commanding improper commutation states, some form of low-pass filtering on HALLA, HALLB, and HALLC is recommended. Passive RC networks generally work well and should be located as close as possible to the device. Figure 2 illustrates these techniques.
VREF VREF
1 k
HALLA
499
HALLB HALLA
1 k
499
HALLA
2.2 nF 2.2 nF
VREF
1 k
HALLA
VREF
1 k
2N2222A HALLB HALLB
1 k
499
HALLB
2.2 nF
2.2 nF
VREF
VREF
1 k
HALLC
499
HALLC
1 k 2.2 nF
HALLC
499
HALLC
2.2 nF
UDG-97182
UDG-97185
Figure 1. Converting Hall Code From 60 to 120
Figure 2. Passive Hall Filtering Technique
8
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
configuring the oscillator The UCC3626 oscillator is designed to operate at frequencies up to 250 kHz and provide a triangle waveform on CT with a peak-to-peak amplitude of 5 V for improved noise immunity. The current used to program CT is derived from the R_TACH resistor according to the following equation: I OSC + 25 Amps R_TACH (1)
The oscillator frequency is set by R_TACH and CT according to the following relationship: f OSC + 2.5 R_TACH CT Hz (2)
Timing resistor values should be between 25 k and 500 k, while capacitor values should be between 100 pF and 1 F. Figure 3 provides a graph of oscillator frequency for various combinations of timing components. As with any high-frequency oscillator, timing components should be located as close as possible to the device pins when laying out the printed-circuit board. It is also important to reference the timing capacitor directly to the ground pin on the UCC3626 rather than daisy chaining it to another trace or the ground plane. This technique prevents switching current spikes in the local ground from causing jitter in the oscillator. synchronizing the oscillator A common system specification is to have all oscillators synchronized to a master clock. The UCC3626 provides a SYNCH input for this purpose. The SYNCH input is designed to interface with a digital clock pulse generated by the master oscillator. A positive-going edge on this input causes the UCC3626 oscillator to begin discharging. In order for the slave oscillator to function properly, it must be programmed for a frequency slightly lower than that of the master. Also, a resistor equal to R_TACH must be placed in parallel with CT. Figure 4 illustrates the waveforms for a slave oscillator programmed to 20 kHz with a master frequency of 30 kHz. The SYNCH pin must be grounded when not used.
OSCILLATOR FREQUENCY vs TIMING CAPACITANCE
1.E+06
R_TACH = 25 k fOSC - PWM Frequency - Hz
1.E+05
R_TACH = 100 k
1.E+04
R_TACH = 250 k R_TACH = 500 k 1.E+03 1.E-09 1.E-07 1.E-08 1.E-10 CT - Oscillator Timing Capacitance - F
Figure 3
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9
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
programming the tachometer The UCC3626 tachometer consists of a precision 5-V monostable, triggered by either a rising or falling edge on any of the three Hall inputs, HALLA, HALLB, and HALLC. The resulting TACH_OUT waveform is a variable duty-cycle square wave whose frequency is proportional to motor speed, as given by: TACH_OUT + V 20 P Hz (3)
where P is the number of motor pole pairs and V is motor velocity in RPM. The on time of the monostable is programmed via timing resistor R_TACH and capacitor C_TACH according to the following equation: t ON + R_TACH C_TACH sec (4)
Figure 5 provides a graph of on times for various combinations of R_TACH and C_TACH. On time is typically set to a value less than the minimum TACH_OUT period as given by: t PERIOD (min) + 20 V MAX P sec (5)
where P is the number of motor pole pairs and V is motor velocity in RPM.
TACHOMETER ON-TIME vs TIMING CAPACITANCE
1.E+00
tON - Tachometer On-Time - s
1.E-01
R_TACH = 500 k
1.E-02
R_TACH = 250 k
SYNCH WITHOUT SYNCH
1.E-03 R_TACH = 100 k 1.E-04
CT WITH SYNCH
1.E-05 R_TACH = 25 k 1.E-06 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
C_TACH - Tachometer Timing Capacitance - F
Figure 4. Oscillator Waveforms
Figure 5
10
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
The TACH_OUT signal can be used to close a digital velocity loop using a microcontroller, as shown in Figure 6, or directly low-pass filtered in an analog implementation, Figure 7.
UCC3626 MC68HC11 PB0-PB7 PC0 AD558 DB0-DB7 VCE 4 5 6 R_TACH C_TACH CT
14 PWM_NI
VCS
VOUT
13 PWM_I
VOUTSENSE VOUTSELECT IC1 3 TACH_OUT
UDG-97188
Figure 6. Digital Velocity Loop Implementation Using MC68HC11 two quadrant vs four quadrant control Figure 8 illustrates the four possible quadrants of operation for a motor. Two-quadrant control refers to a system in which operation is limited to quadrants I and III (where torque and velocity are in the same direction). With a two-quadrant brushless dc amplifier, there are no provisions other than friction to decelerate the load, limiting the approach to less demanding applications. Four-quadrant controllers, on the other hand, provide controlled operation in all quadrants, including II and IV, where torque and rotation are of opposite direction.
UCC3626 2 4 5 6 14 - + 3 TACH_OUT VREF R_TACH C_TACH CT CCW PWM_NI VELOCITY CW
II III
I IV
TORQUE CW
13
PWM_I
CCW
UDG-97189 UDG-01118
Figure 7. Simple Analog Velocity Loop
Figure 8. Four Quadrants of Operation
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11
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
When configured for two-quadrant operation, (QUAD=0), the UCC3626 modulates only the low-side devices of the output power stage. The current paths within the output stage during the PWM on- and off-times are illustrated in Figure 9. During the on interval, both switches are on, and current flows through the load down to ground. During the off time, the lower switch is shut off, and the motor current circulates through the upper half bridge via the flyback diode. The motor is assumed to be operating in either quadrant I or III. If operation is attempted in quadrants II or IV by changing the DIR bit and reversing the torque, switches 1 and 4 are turned off and switches 2 and 3 turned on. Under this condition motor current very quickly decays, reverses direction and increases until the control threshold is reached. At this point, switch 2 turns off and current once again circulates in the upper half bridge. However, in this case, the motor's BEMF is in phase with the current, (i.e. the motor's direction of rotation has not yet changed.) Figure 10 illustrates the current paths when operating in this mode. Under these conditions there is nothing to limit the current other than motor and drive impedance. These high-circulating currents can result in damage to the power devices in addition to high, uncontrolled torque.
VMOT VMOT
S1
S3 IOFF IPHASE
S5
S1 IOFF
S3
S5
IPHASE
+ BEMF - ION
+ BEMF -
ION S2 S4 S6 S2 S4 S6
UDG-01119
UDG-01120
Figure 9. Two-Quadrant Chopping
Figure 10. Two-Quadrant Reversal
12
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
By pulse width modulating both the upper and lower power devices (QUAD=1), motor current always decays during the PWM off time, eliminating any uncontrolled circulating currents. In addition, current always flows through the current sense resistor, providing a suitable feedback signal. Figure 11 illustrates the current paths during a four-quadrant torque reversal. Motor drive waveforms for both two- and four-quadrant operation are illustrated in Figure 12.
VMOT
S1
S3
S5
IPHASE
+ BEMF -
IOFF ION S2 S4 S6
UDG-01121
Figure 11. Four-Quadrant Reversal
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13
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
ROTOR POSITION IN ELECTRICAL DEGREES 0 60 120 180 240 300 360 420 480 540 600 660 720
H1 SENSOR INPUTS H2 H3 Code HIGH SIDE AHI OUTPUTS QUAD=0 BHI CHI 101 100 110 010 011 001 101 100 110 010 011 001
ALO LOW SIDE OUTPUTS BLO QUAD=0 CLO + A 0 - MOTOR PHASE B CURRENTS QUAD=0 + 0 - + C 0 - HIGH SIDE AHI OUTPUTS QUAD=1 BHI CHI
ALO LOW SIDE OUTPUTS BLO QUAD=1 CLO + A 0 - MOTOR PHASE B CURRENTS QUAD=1 + 0 - + C 0 - 100% Duty Cycle PWM 50% Duty Cycle PWM
UDG-97190
Figure 12. Motor Drive and Current Waveforms for Two-Quadrant (QUAD=0) and Four-Quadrant (QUAD=1) Operation
14
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
power stage design considerations The flexible architecture of the UCC3626 requires the user to pay close attention to the design of the power output stage. Two- and four-quadrant applications not requiring the brake function are able to use the power stage approach illustrated in Figure 13a. In many cases the body diode of the MOSFET can be used to reduce parts count and cost. If efficiency is a key requirement, Schottky diodes can be used in parallel with the switches.
UDG-97190
VMOT
VMOT
VMOT
TO
TO
TO
MOTOR
MOTOR
MOT
CURRENT SENSE
CURRENT SENSE
CURRENT SENSE
(a)
TWO QUADRANT (a) (b) (c) YES YES YES FOUR QUADRANT YES NO YES
(b)
SAFE BRAKING NO YES YES POWER REVERSAL Four-Quad Only No Four-Quad Only PULSE-BYPULSE YES YES YES
(c)
CURRENT SENSE AVERAGE YES NO YES
UDG-01122
Figure 13. Power Stage Topologies If the system requires a braking function, diodes must be added in series with the lower power devices and the lower flyback diodes must be returned to ground, as pictured in Figure 13b, and 13c. This requirement prevents brake currents from circulating in the lower half bridge and bypassing the sense resistor. In addition, the combination of braking and four-quadrant control necessitates an additional resistor in the diode path to sense current during the PWM off time as illustrated in Figure 13c.
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15
UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
current sensing The UCC3626 includes a differential current-sense amplifier with a fixed gain of five, along with an absolute value circuit. The current-sense signal should be low pass filtered to eliminate leading-edge spikes. In order to maximize performance, the input impedance of the amplifier should be balanced. If the sense voltage must be trimmed for accuracy reasons, a low-value input divider or a differential divider should be used to maintain impedance matching, as shown in Figure 14.
RF SNS_NI RADJ RS RF SNS_I RADJ << RF (a) (b)
UDG-01123
RF RF RADJ CF RS RF SNS_I CF SNS_NI
Figure 14. (a) Differential Divider and (b) Low-Value Divider With four-quadrant chopping, motor current always flows through the sense resistor. However, during the flyback period the polarity across the sense resistor is reversed. The absolute value amplifier cancels the polarity reversal by inverting the negative sense signal during the flyback time, see Figure 15. Therefore, the output of the absolute value amplifier is a reconstructed analog of the motor current, suitable for protection as well as feedback loop closure.
VMOT Ip Is
S1
S3
S5
IPHASE
Ip If
+ BEMF -
IOFF ION S2 S4 S6 Im
5*Ip
Is
X5 Im
UDG-01124
If
Figure 15. Current Sense Amplifier Waveform
16
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UCC2626, UCC3626
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
APPLICATION INFORMATION
Figure 17 illustrates a simple 175-V, 2-A, two-quadrant velocity controller using the UCC3626. The power stage is designed to operate with a rectified off-line supply using IR2210s to provide the interface between the low voltage control signals and the power MOSFETs. The power topology illustrated in Figure 13c is implemented in order to provide braking capability.
SIGN/MAGNITUDE CONVERTER 10 k 10 k 10 k 10 k
11
IOUT
VELOCITY COMMAND 5V
- U1 +
- U5 + 10 k - U6 +
- U8 + CURRENT MAGNITUDE U7 CURRENT SIGN CURRENT ERROR AMPLIFIER
13
PWM_I
21
DIR
BIPOLAR 10 k TACH GAIN - U3 +
10 k TACHOMETER FILTER 3 TACH_OUT
4.99 k
4.99 k
- U2 +
2N7002 8 DIR_OUT
UDG-99061
Figure 16. Four-Quadrant Control Loop The controller's speed command is set by potentiometer R30, while the speed feedback signal is obtained by low-pass filtering and buffering the TACH_OUT signal using R11 and C9. Small signal compensation of the velocity control loop is provided by amplifier U5A, whose output is used to control the PWM duty cycle. The integrating capacitor, C8, places a pole at 0 Hz and a zero in conjunction with R10. This zero can be used to cancel the low-frequency motor pole and to cross the loop-over with a -20 dB gain response. Four-quadrant applications require the control of motor current. Figure 16 illustrates a sign/magnitude current control loop within an outer bipolar velocity loop using the UCC3626. U1 serves as the velocity loop error amplifier and accepts a 5-V command signal. Velocity feedback is provided by low-pass filtering and scaling the TACH_OUT signal using U2. The direction output switch, DIR_OUT, and U3 set the polarity of the tachometer gain according to the direction of rotation. The output of the velocity error amplifier, U1, is then converted to sign/magnitude form using U5 and U6. The sign portion is used to drive the DIR input while the magnitude commands the current error amplifier, U8. Current feedback is provided by the internal current sense amplifier via the IOUT pin.
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17
18
U2 VREF IR2110 9 VDD VB R16 47 Q1 IRF730 C22 10 F MOTOR PHASE A HO VS NC +12V D8 1N5418 VCC COM C13 0.1 F R18 47 2 R17 D2 10 1N4148 Q2 IRF730 3 D16 11DF4 4 D7 MUR1520 5 C12 0.1 F 7 NC U1 VREF +12V 28 VDD R2 1 k R3 1 k VREF C2 0.1 F 2 1 15 HALLA 16 HALLB 13 VSS LO 17 HALLC 20 QUAD SNS_NI VREF 21 DIR_IN 9 VB HO VS NC VCC COM 4 3 2 C16 0.1 F 13 VSS VREF R10 C8 R12 250 k U3 VREF IR2110 9 C17 0.1 F VREF C9 0.1 F R13 35 k R14 15 k 8 VDD NC 10 HIN 12 LIN 11 SD 14 NC VB HO VS NC VCC COM 6 7 5 4 3 2 C19 0.1 F 13 VSS LO 1 R30 2 k C23 0.1 F R27 0.1 R31 2 k R28 0.1 D18 11DF4 C18 0.1 F D13 MUR1520 +12V D15 1N5418 R25 D6 10 1N4148 R18 47 Q2 IRF730 MOTOR PHASE C R11 160 k LO 1 5 7 C15 0.1 F D10 MUR1520 +12V D17 11DF4 MOTOR PHASE B C14 0.1 F 8 10 HIN 7 SYNCH C10 3900 pF 12 LIN 11 SD 14 PWN_IN TACH_OUT 14 NC C7 13 PWM_I DIR_OUT 8 3 CT RTACH 4 C6 100 pF 6 IOUT 11 NC VDD 6 19 BRAKE 18 COAST CTACH 5 OC_REF 12 SNS_I 10 IR2110 R19 10 R7 10 k R8 10 k R9 10 k 9 U3 CLOW 22 1 BLOW 24 ALOW 26 14 NC GND CHI 23 11 SD VREF BHI 25 12 LIN C1 0.1 F R4 R5 499 C5 2200 pF VREF C4 2200 pF C3 2200 pF 499 AHI 27 10 HIN UCC3626 C11 0.1 F 8 6 R15 10 D1 1N4148 VMOT
UCC2626, UCC3626
R1 1 k
FROM HALL SENSORS
SLUS318B - APRIL 1999 - REVISED JANUARY 2002
R6 499
D3 1N4148 VMOT R20 47 Q3 IRF730
C21 10 F
APPLICATION INFORMATION
Figure 17. Two-Quadrant Velocity Controller
R21 D4 10 1N4148 R22 47
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+ SPEED SET R29 + U5A 1/2 LM358 U5B 1/2 LM358
D11 1N5418
Q4 IRF730 R23 10 D5 1N4148 VMOT R24 47 Q5 IRF730
R30 10 k
C20 10 F
UDG-01117
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